In recent years, the demands for downsizing and performance enhancement in electronic devices are expanding more and more. The key devices that determine the downsizing and performance enhancement are LSIs (Large Scale Integration) mounted on devices.
Along with progress in microfabrication techniques, the performance of LSIs has been improved by integrating more transistors on one chip. However, due to influences of limitations in miniaturization, increase in usage cost of most-advanced processes etc., advancing integration onto one chip as is conventionally done is not always an optimal solution. Therefore, integration in three-dimensional directions implemented by stacking a plurality of LSIs is a promising technique.
FIG. 14 illustrates an LSI composed by combining a large number of logic circuits. The LSI 1 is equipped with processor units (PU1, PU2), a memory controller (MEMC), a peripheral circuit (PERI) such as an interrupt controller, and a bus (BUS) mutually connecting signals thereof. A crystal oscillator (Crystal), which supplies a reference clock signal, is installed outside of the LSI 1. The interior of the LSI 1 is equipped with a PLL circuit (PLL), which multiplies the frequency of the reference clock signal, and a clock pulse generator (CPG), which appropriately subjects the PLL output clock signal to frequency dividing and distributes clock signals to the circuit blocks of PU1, PU2, MEMC, and PERI. These circuit blocks are connected to the bus (BUS) by wiring (SI1, SI2, SI3, SI4). Thus, information can be mutually transmitted among PU1, PU2, PERI, and MEMC. PU1, PU2, PERI, and MEMC have a configuration in which a large number of logic circuits are combined as illustrated in FIG. 15. The clock signals supplied to flip-flop circuits of these logic circuits are supplied by clock wiring (CLK_PU, CLK_BUS, CLK_MEMC, CLK_PERI).
FIG. 15 is a diagram illustrating the logic circuit used in
FIG. 14, which is formed in one chip. This logic circuit is composed of the plurality of flip-flop circuits (FF), a combinational circuit (Comb), clock wiring (CLK1), input ports (IN1, IN2, IN3), and output ports (OUT1, OUT2, OUT3). The logic circuit operates in synchronization with the clock signal. More specifically, the signals of IN1 to IN3 are latched by the flip-flop circuits at the rising or falling edge of the clock signal and input to the combinational circuit, which is in a subsequent stage. The results of computations carried out in the combinational circuit are latched by the flip-flop circuits of a subsequent stage at next rising and falling edges of the clock signal and output to OUT1 to OUT3. As described above, this operation is executed in synchronization with the clock signals distributed to the flip-flops. In other words, the computations are synchronized. Therefore, when the phases of the clock signals distributed to the flip-flops are mutually shifted, malfunctions are caused, for example, the flip-flops of the subsequent stage cannot latch correct signals. This shift in the phase of the clock signals is generally called clock skew.
In Japanese Patent Application Laid-Open Publication No. 2008-047768 (Patent Document 1), as a method of reducing the clock skew, a technique of stacking an LSI composed only of flip-flop circuits and clock wiring and an LSI composed only of combinational logic circuits is mentioned.